1. Field of the Invention
The present invention relates to a memory device and more particularly to an equalization signal generator for a semiconductor memory device.
2. Background of the Related Art
As shown in FIG. 1, a related art equalization signal generator includes a plurality of address buffers AB0, . . . ,ABn and address transition detectors AD0-ADn, and address transition detection (ATD) signal adder 10, and an equalization signal generating unit 20. A corresponding one of the plurality of address buffers AB0-ABn respectively receives a corresponding one of a plurality of address signals ADD0-ADDn. The plurality of address transition detectors AD0-ADn receives signals outputted from the address buffers AB0-ABn. The address transition detection (ATD) signal adder 10 sums respective address transition detection signals ATD0-ATDn from address transition detectors AD0-ADn. The equalization signal generating unit 20 receives a signal ATDS outputted from the adder 10 and outputs an equalization signal EQ.
FIG. 2 illustrates a detailed stricture of the address transition detection signal adder 10 and the equalization signal generating unit 20 in the equalization signal generator of FIG. 1. Three address signals ADD0, ADD1, ADD2 will be selected from the plurality of address signals ADD0-ADDn for convenience.
As shown, the address transition detecting signal adder 10 includes a NOR gate for NORing the address transition detection signals ATD0, ATD1, ATD2 and outputting the address transition detection signal ATDS. The equalization signal generator 20 includes a delay unit 30 having a plurality of serially connected inverters I1-In for delaying the signal ATDS outputted from the address transition detection signal adder 10, and a NAND gate for NANDing a delayed signal DEL outputted from the delay unit 30 and the signal ATDS outputted from the address transition detection signal adder 10.
As shown in FIGS. 3A through 3C, the respective address transition detection signals ATD0, ATD1, ATD2 are NORed in the NOR gate of the adder 10, and the signal ATDS is outputted from the NOR gate as shown in FIG. 3E. At this time, when at least one of the address transition detection signals ATD0, ATD1, ATD2 is at a high level, the signal ATDS is rendered to be a low level. In order to render the signal ATDS to be a high level, the applied address transition detection signals ATD0, ATD1, ATD2 should be at a low level.
The signal ATDS is applied to the delay unit 30 and the NAND gate in the equalization generating unit 20 for outputting the equalization signal EQ, as shown in FIG. 3F. Because the size of the transistors in the inverters I1-I4 are different, the delay signal DEL serving as an output signal of the delay unit 30 is delayed for a longer time when the signal ATDS applied to the delay unit 30 is turned from a low level to a high level than when the signal ATDS is turned from a high level to a low level.
Therefore, when the signal ATDS is turned from a high level to a low level, the delay signal DEL is rendered to be a low level as shown in FIG. 3E. When the signal ATDS is turned from a low level to a high level, the equalization signal EQ remains at a high level due to the longer delay of the ATDS signal through the delay unit 30 for appropriately carrying out an equalization operation.
However, as shown in FIGS. 4A through 4C, when a pulse width of the equalization signal is decreased in order to accomplish a faster semiconductor chip operation, and although a single address transition detection signal is applied, a sufficient pulse width TD is not secured as shown in FIG. 4F, whereby a normal equalizing operation may not be properly carried out. Further, when a plurality of address transition detection signals are applied, the pulse width of the equalization signal becomes unnecessarily wide, thereby resulting in an abnormal chip operation.